Computer Engineering and Applications ›› 2020, Vol. 56 ›› Issue (13): 181-188.DOI: 10.3778/j.issn.1002-8331.1909-0034

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FPGA Implementation of Convolution Neural Network Digital Recognition System

SUN Jingcheng, WANG Zhengyan, LI Zenggang   

  1.  School of Electronic Information, Qingdao University, Qingdao, Shandong 266071, China
  • Online:2020-07-01 Published:2020-07-02



  1. 青岛大学 电子信息学院,山东 青岛 266071


The classical network model of digital recognition is mainly BP neural network and convolution neural network. Compared with convolution neural network, the recognition effect of convolution neural network is better, and it is more suitable to deal with the problem of image recognition. At present, convolution neural networks are mostly implemented by software, and hardware has the advantages of parallelism and high speed. Therefore, this paper intends to use hardware description language(Verilog) to implement convolution neural network, in order to ensure high recognition rate, fully tap the advantages of hardware implementation. By studying the working principle and structure of the network, the complete circuit model is constructed, and the implementation scheme of Field Programmable Gate Array(FPGA) is given. Convolution neural network trains 60?000 digital sample images in MNIST database through back propagation, extracts the weight and offset with the highest accuracy, and then carries on the forward propagation of the network to complete the digital recognition. The complete process is realized with the help of ModelSim and Quartus II simulation tools. The results show that all the samples take 50?ms to train under the 100?MHz clock. Compared with the software implementation, the speed is obviously improved, the real-time performance of the hardware design is satisfied, and the accuracy is up to 95.4%. This research provides a method and strategy for image recognition of embedded devices, and has practical application value.

Key words: convolution neural network, Verilog, Field Programmable Gate Array(FPGA), MNIST database, number recognition


数字识别所依靠的经典网络模型主要为BP神经网络和卷积神经网络。相比较,卷积神经网络的识别效果更好,更适合处理图像识别问题。目前,卷积神经网络多为软件实现,而硬件有着并行性与速度快的优点。因此,意图以硬件描述语言(Verilog)实现卷积神经网络,在保证在高识别率的情况下,充分挖掘硬件实现的优点。通过研究网络的工作原理及结构,构造完整电路模型,给出了现场可编程门阵列(Field-Programmable Gate Array,FPGA)的实现方案。卷积神经网络通过反向传播训练MNIST数据库中60?000幅数字样本图片,提取准确率最高的权重与偏置,再进行网络的前向传播,完成数字识别。完整过程借助ModelSim和Quartus II仿真工具实现。仿真结果表明,全部样本在100?MHz时钟下训练耗时50?ms,相较软件实现而言,速度明显提高,满足硬件设计的实时性,且准确率较高,可达95.4%。该研究为应用于嵌入式设备的图像识别提供了方法和策略,具有实际应用价值。

关键词: 卷积神经网络, Verilog, 现场可编程门阵列(FPGA), MNIST数据库, 数字识别