Computer Engineering and Applications ›› 2020, Vol. 56 ›› Issue (6): 271-278.DOI: 10.3778/j.issn.1002-8331.1902-0035

Previous Articles    

Test Strategy for 2.5D ICs Using Auxiliary Interposer and E-Fuse

LIU Jun, WANG Xiuyun, REN Fuji   

  1. 1.School of Computer and Information, Hefei University of Technology, Hefei 230009, China
    2.Anhui Province Key Laboratory of Affective Computing and Advanced Intelligent Machine, School of Computer and Information, Hefei University of Technology, Hefei 230009, China
    3.Department of Information Science & Intelligent Systems, Faculty of Engineering, The University of Tokushima, Tokushima 7708502, Japan
  • Online:2020-03-15 Published:2020-03-13

使用辅助转接板和熔丝的2.5D集成电路测试策略

刘军,王秀云,任福继   

  1. 1.合肥工业大学 计算机与信息学院,合肥 230009
    2.合肥工业大学 计算机与信息学院 情感计算与先进智能机器安徽省重点实验室,合肥 230009
    3.德岛大学 工学院 智能信息系,日本 德岛 7708502

Abstract:

Pre-bond testing of interposers has an important impact on the yield of 2.5D integrated circuits. To improve the fault coverage of interposers and reduce the test cost, a new technique for testing the open-fault and short-fault on the interconnect wires is proposed, which only employs one auxiliary interposer. The presented technique firstly divides the interconnect wires into several groups by the algorithm which can find the largest independent set in an adjacency matrix. The interconnect wires within one group will not generate short faults. After grouping, the wires are added on the auxiliary interposer to connect the intra-group wires. Then e-fuse is added on the auxiliary interposer via the presented the e-fuse connection strategy to connect inter-group wires. The presented connection strategy of inter-group e-fuse can maximize the number of parallel test loops and minimize the number of required e-fuse. During the test, the open-fault testing is firstly performed. After the open-fault test, the e-fuse on the auxiliary interposer will be blown and the short-fault testing will be conducted. Experimental results show that the proposed technique can effectively increase the open-fault and short-fault coverage, and reduce the hardware cost.

Key words: 2.5D, silicon interposer, e-fuse, fault coverage

摘要:

绑定前转接板的测试对2.5D集成电路的成品率有重要影响。为提高绑定前转接板的测试故障覆盖率,并减少测试成本,提出了仅使用一块辅助转接板针对待测试转接板中的互连线进行开路和短路故障测试的新方案。该方案首先使用邻接矩阵求极大独立集的方法将待测试转接板上的互连线进行分组,使得每组内的互连线不会发生短路故障。分组完成后,在辅助转接板上布置导线,实现互连线的组内连接。接着使用所提出的分组间熔丝连接策略在辅助转接板上布置熔丝,将互连线进行组间连接,最大化可以对开路故障进行并行测试的测试路径数量,并且减少所需的熔丝数量。测试时,首先进行开路故障的测试。待开路故障测试完成,将辅助转接板上的熔丝熔断,再进行短路故障测试。实验结果表明,所提方案有效地提高了开路故障和短路故障的覆盖率,并且减少了硬件开销。

关键词: 2.5D, 转接板, 熔丝, 故障覆盖率