Computer Engineering and Applications ›› 2018, Vol. 54 ›› Issue (4): 25-30.DOI: 10.3778/j.issn.1002-8331.1711-0233

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Optimizing adaptive run-time reconfigurable cache

HU Sensen, SU Jiafu   

  1. Chongqing Technology and Business University, Chongqing 400067, China
  • Online:2018-02-15 Published:2018-03-07



  1. 重庆工商大学,重庆 400067

Abstract: Dynamically reconfigurable cache has a significant advantage in the scope of resource utilization and power consumption due to the reconfiguration of cache capacity, structure, mapping rules at run-time. In view of the characteristics of the dynamic issue-width of the VLIW processor, this paper uses its dynamic features to drive the resizing cache during run-time. In such a manner, the data path can be allocated well so as to split and merge cores dynamically. This is different from the traditional approaches that monitor the cache’s miss rate. To further smoothen the performance of reconfigurable cache in the frequent scenario, a novel, and simple cache strategy is proposed. Thus, it ensures a smooth cache performance from one cache size to the other. The simulation results show that the method can achieve an average decrease of 16% during the 2 000 cycles after cache reconfiguration occurs, and the whole performance is improved.

Key words: Very Long Instruction Word(VLIW), cache resizing, reconfiguration cache, issue-width

摘要: 动态可重构缓存由于能够在运行时进行缓存容量、结构、映射规则等方面的重新配置,因而在资源利用率和能耗方面有很大优势。针对超长指令字处理器发射宽度动态变化的特点,提出了在运行时利用其动态特征来驱动缓存的重构,从而达到动态分离或合并处理器核的目的。这不同于传统的以缓存缺失率来驱动缓存重构的方法。为了平滑频繁重构场景下缓存的性能,进一步提出了一种重构时的过渡机制,使缓存平滑地从一种配置过渡到另一种配置。设计了实验并对重构策略进行了性能评估,仿真结果表明,该方法可以实现在重构后2 000周期内,缓存缺失率平均下降16%,并且提高了系统性能。

关键词: 超长指令字, 缓存重构, 可重构缓存, 发射宽度