Abstract: In high-speed serial interface design of PCIE2.0, in order to make data transmission more accurately, the working clock which serial transferred data needs should be locked in a very short time. In order to reduce PLL lock time and improve clock stability, a new binary searching algorithm automatic frequency calibration circuit is proposed based on traditional sequential searching algorithm circuit and applied in the 5 GHz frequency synthesizer. The maximum correction time is 22.5 μs. Frequency synthesizer is taped out in SMIC 55 nm CMOS process, under SS corner, the area of automatic frequency calibration circuit is only 0.0013 mm2. After testing, PLL can lock in a short time and has a perfect performance.

Key words: Phase Locked Loop（PLL）, Automatic Frequency Calibration（AFC）, sequential search, binary search, lock time

摘要： 在高速串行接口PCIE2.0的设计中，为了保证数据传输的正确性，数据串行传输的工作时钟需要在很短的时间内完成锁定。为了减小锁相环的锁定时间，提高时钟稳定性，在传统的顺序搜索自动频率校正算法电路的基础上，提出了一种新的二进制搜索算法校正电路，并且应用于5 GHz的锁相环中，最大校正时间为22.5 μs。锁相环在SMIC 55 nm CMOS工艺下流片，SS工艺角下，AFC电路的面积为0.001 3 mm2。经测试，锁相环能够快速锁定，性能良好。

关键词: 锁相环（PLL）, 自动频率校正（AFC）, 顺序搜索, 二进制搜索, 锁定时间