FPGA implementation of “One Frame One Key” encryption/decryption solution suitable for CCSDS

Computer Engineering and Applications ›› 2015, Vol. 51 ›› Issue (10): 84-88.

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FPGA implementation of “One Frame One Key” encryption/decryption solution suitable for CCSDS

LIU Lan1, YAO Xingzhong2, WANG Zhenyu1, YANG Xiaofei1

1.School of Optical and Electronic Information, Huazhong University of Science and Technology, Wuhan 430074, China
2.Laboratory of Precision-Guided Technology, Second Artillery Command College, Wuhan 430012, China

Online:2015-05-15 Published:2015-05-15

适用于CCSDS的“一帧一密”加/解密方案的FPGA实现

刘兰1，姚行中2，王振宇1，杨晓非1

1.华中科技大学光学与电子信息学院，武汉 430074
2.第二炮兵指挥学院精确制导技术实验室，武汉 430012

Abstract

Abstract: Encryption plays an important role in satellite data transmission systems, especially satellite and ground data transmission. It realizes an encryption/decryption solution for CCSDS. The system is designed based on Xilinx Spartan6 FPGA, AES encryption algorithm and the CTR operation mode. The design is able to realize data encryption less than block size without generating redundant data, overcome the limitation of the block encryption algorithm to encrypt the fixed block size data. The paper puts forward the encryption scheme of “one frame one key” to improve the security of the algorithm. Pipeline and logical multiplex are used in the system to improve speed and save chip resources. Under the clock frequency of 33 MHz, encryption and decryption speed are up to 264 Mb/s.

Key words: Advanced Encryption Standard（AES）, Counter（CTR）, one frame one key, encryption/decryption, Field Programmable Gate Array（FPGA）

摘要： 加密是卫星数据传输系统特别是卫星星地数据传输系统的重要组成部分。设计了一种针对CCSDS标准的加/解密方案，该系统以Xilinx Spartan 6开发板为开发平台，以AES为核心加密算法，CTR模式为工作模式，能实现对少于块大小的数据的加密而不产生冗余数据，克服了分组加密算法只能对固定块大小的数据进行加密的局限性。提出“一帧一密”的加密方案，能有效提高算法的安全性。算法中采用的流水线结构和逻辑复用方法，能有效提高速度与节省芯片资源。在33 MHz时钟下测试，系统加密速度和解密速度都能达到264 Mb/s。

关键词: 高级加密标准（AES）, 计算器模式, 一帧一密, 加/解密, 现场可编程门阵列

LIU Lan1, YAO Xingzhong2, WANG Zhenyu1, YANG Xiaofei1. FPGA implementation of “One Frame One Key” encryption/decryption solution suitable for CCSDS[J]. Computer Engineering and Applications, 2015, 51(10): 84-88.

刘兰1，姚行中2，王振宇1，杨晓非1. 适用于CCSDS的“一帧一密”加/解密方案的FPGA实现[J]. 计算机工程与应用, 2015, 51(10): 84-88.

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FPGA implementation of “One Frame One Key” encryption/decryption solution suitable for CCSDS

适用于CCSDS的“一帧一密”加/解密方案的FPGA实现

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