Abstract: Multi-core technology has become the inevitable trend of current processor architecture. It is an efficient and sufficient functional verification of the multi-core design that has become one of the hot points in IC design and verification fields, and also one of the key factors to the success final tape-out. Different from the common verification pattern based on emulation, this paper pays more attention in highlighting the overall functional verification environment design driven with the coverage functional verification strategy to verify RISC multi-core processor, and putting forward the idea of “passive authentication” with hardware and software co-verification strategy, ultimately achieves the goal of “single instruction comparison”. Timing verification and power evaluation strategies are also introduced in the later validation stage, providing a complete verification solution for the RISC multi-core processor.

Key words: multi-core processor, functional verification, coverage, timing verification, power evaluation

摘要： 众核技术已成为当前处理器体系结构发展的必然趋势，如何对众核处理器设计进行有效而充分的验证，成为当今IC设计验证领域的研究热点之一，也是众核处理器芯片能否成功流片的关键因素之一。目前工业界采用基于仿真的验证作为主要的验证方式，重点介绍了以覆盖率为导向的RISC众核处理器的功能验证环境的整体设计，提出了“被动式”的验证思想，并采用“软硬件协同验证”的策略，最终达到每条指令都比对通过的验证目标，辅以后期阶段所引入的时序验证策略和功耗评估策略，完整地提出了一套芯片验证平台搭建和验证功能实现的方法流程。

关键词: 众核处理器, 功能验证, 覆盖率, 时序验证, 功耗评估