Abstract: This paper presents the structure and implementation of an adaptive low-pass filter system based on ADPLL（All Digital Phase Locked Loop）. The input signal is converted into square signal after shaping. The square signal is phase-
locked and transformed into synchronous frequency multiplication signal after passing through the ADPLL based on FPGA. The frequency multiplication signal is input into switched-capacitor filter MAX295 as clk which can control corner frequency. The cutoff frequency of the low-pass filter is tracked automatically with the change of signal frequency. The design principle is introduced. The design method of ADPLL and phase-locked frequency multiplier based on FPGA is analyzed in detail. The experiment results illustrate that the system is feasible and effective. The system is able to realize the self-tracking of double-frequency and filtering when the frequency varies from 1 kHz to 50 kHz.

Key words: Field-Programmable Gate Array（FPGA）, All Digital Phase Locked Loop（ADPLL）, adaptive, switched-capacitor filter, low pass filter

摘要： 提出了一种新的基于全数字锁相环的自适应低通滤波系统的结构和实现方法。输入信号经整形后产生方波信号，方波信号经FPGA实现的全数字锁相环锁相同步倍频后，再将同步倍频信号输入到开关电容滤波器MAX295的时钟输入端，通过该时钟信号来控制滤波器的截止频率，从而实现滤波器频率的自动跟踪。介绍了系统设计原理，详细分析了FPGA实现全数字锁相环和锁相倍频的设计方法。通过实验验证了该系统的可行性和有效性，能够实现1 kHz至50 kHz的频率自跟踪倍频和滤波。

关键词: 现场可编程门阵列（FPGA）, 全数字锁相环, 自适应, 开关电容滤波, 低通滤波器