Reconfigurable multiprocessor system-on-chip： survey of architecture

Computer Engineering and Applications ›› 2012, Vol. 48 ›› Issue (20): 39-45.

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Reconfigurable multiprocessor system-on-chip： survey of architecture

TANG Liu1，2, HUANG Zhangqin1, HOU Yibin1, FANG Fengcai2

1.Embedded Software and Systems Institutes, Beijing University of Technology, Beijing 100124, China
2.Guangxi Teachers Education University, Nanning 530023, China

Online:2012-07-11 Published:2012-07-10

可重构多核片上系统体系结构综述

唐柳1，2，黄樟钦1，侯义斌1，方凤才2

1.北京工业大学嵌入式软件与系统研究所，北京 100124
2.广西师范学院，南宁 530023

Abstract

Abstract: Reconfigurable multiprocessor system on chip combines the high performance of hardware with the flexibility of software. It effectively and efficiently exploits all sorts of parallelism by involving different granularity and differently coupled reconfigurable resources. Simultaneously, it reduces the design and development costs and shortens the time to market. In this paper, the concept and major classes are introduced. Subsequently, the hardware architecture of reconfigurable multiprocessor system on chip at the system level is reviewed. The future research trends and key problems are discussed.

Key words: reconfigurable, multiprocessor system-on-chip, architecture, dependability

摘要： 可重构片上多核系统利用不同粒度、不同耦合度的可重构资源，充分开发资源的并行性，兼顾硬件计算的高性能及软件实现的灵活性，且复用特性使其具备开发设计成本降低、产品面市时间缩短的优势。介绍可重构计算系统概念及其分类，从系统级层面回顾可重构多核片上系统体系结构的研究进展，讨论未来的研究趋势及需要关注的关键问题。

关键词: 可重构, 多核片上系统, 体系结构, 可信性

TANG Liu1，2, HUANG Zhangqin1, HOU Yibin1, FANG Fengcai2. Reconfigurable multiprocessor system-on-chip： survey of architecture[J]. Computer Engineering and Applications, 2012, 48(20): 39-45.

唐柳1，2，黄樟钦1，侯义斌1，方凤才2. 可重构多核片上系统体系结构综述[J]. 计算机工程与应用, 2012, 48(20): 39-45.

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Reconfigurable multiprocessor system-on-chip： survey of architecture

可重构多核片上系统体系结构综述

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