Differential Power Analysis resistant hardware implementation of AES cryptosystem

doi:10.3778/j.issn.1002-8331.2009.36.019

Computer Engineering and Applications ›› 2009, Vol. 45 ›› Issue (36): 63-65.DOI: 10.3778/j.issn.1002-8331.2009.36.019

• 研发、设计、测试 • Previous Articles Next Articles

Differential Power Analysis resistant hardware implementation of AES cryptosystem

ZOU Cheng，ZHANG Peng，DENG Gao-ming，ZHAO Qiang

Department of Computer Engineering，Ordnance Engineering College，Shijiazhuang 050003，China

Received:2008-12-29 Revised:2009-02-16 Online:2009-12-21 Published:2009-12-21
Contact: ZOU Cheng

AES密码电路抗差分功耗分析设计

邹程，张鹏，邓高明，赵强

军械工程学院计算机工程系，石家庄 050003

通讯作者: 邹程

Abstract

Abstract: This paper firstly declares the principle of the Differential Power Analysis（DPA） attack technology，and shows the vulnerability for power analysis attack straightforward AES.Then，it gets the method about masking to reduce the differential power signal of an AES circuit and completes the circuit.Finally，with experiment，it proves this circuit can lead to the failure of differential power analysis.

摘要： 针对差分功耗分析（DPA）攻击的原理及特点，分析了高级加密标准（AES）的DPA攻击弱点，采用掩盖（Masking）的方法分别对AES算法中字节代换部分（SubBytes）及密钥扩展部分进行了掩盖，在此基础上完成了AES抵御DPA攻击的FPGA硬件电路设计。通过对该AES的FPGA电路的差分功耗攻击实验验证，该方法能够很好地抵抗DPA攻击。

CLC Number:

TP309

ZOU Cheng，ZHANG Peng，DENG Gao-ming，ZHAO Qiang. Differential Power Analysis resistant hardware implementation of AES cryptosystem[J]. Computer Engineering and Applications, 2009, 45(36): 63-65.

邹程，张鹏，邓高明，赵强. AES密码电路抗差分功耗分析设计[J]. 计算机工程与应用, 2009, 45(36): 63-65.

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Differential Power Analysis resistant hardware implementation of AES cryptosystem

AES密码电路抗差分功耗分析设计

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