Research and design of embedded general image enhancement chip

doi:10.3778/j.issn.1002-8331.2008.26.022

Computer Engineering and Applications ›› 2008, Vol. 44 ›› Issue (26): 74-76.DOI: 10.3778/j.issn.1002-8331.2008.26.022

• 研发、设计、测试 • Previous Articles Next Articles

Research and design of embedded general image enhancement chip

ZHAO Jun,ZHANG Ke-huan,LI Ren-fa

School of Computer and Communications，Hunan University，Changsha 410082，China

Received:2007-11-05 Revised:2008-01-16 Online:2008-09-11 Published:2008-09-11
Contact: ZHAO Jun

嵌入式通用图形加速芯片的研究与设计

赵俊,张克环,李仁发

湖南大学计算机与通信学院，长沙 410082

通讯作者: 赵俊

Abstract

Abstract: A new technique of design and implemention of embedded general image enhancement chip is introduced in the paper.The chip helps microprocessor finish displaying task and lightens the work burden of microprocessor，it not only increases the speed of image processing but also improves the system’s response and real-time.This image enhancement chip has general control bus，data bus and address bus，it can communicate with different embedded microprocessor，and can be direct accessed by the microprocessor as parts of microprocessor’addressing space.The system of the chip is analyzed，and the function of each module is discussed in detail.It is verified on FPGA，the result is proved that the design achieves the goals expected.

Key words: embedded microprocessor, image enhancement chip, Field Programmable Gate Array（FPGA）

摘要： 研究并设计实现了一种嵌入式通用图形加速芯片。该芯片将图形图像的显示功能完全用硬件逻辑电路实现，把嵌入式微处理器从繁重的图形图像显示处理任务中解放出来，不但提高了图形图像的处理速度，而且改善了系统响应速度和实时性。另外，芯片具有通用的数据、地址和控制总线，能与各种不同的嵌入式微处理器通信，并能作为微处理器寻址空间的一部分而被直接访问，因而具有很强的通用性。详细分析了该图形加速芯片的总体结构设计和各模块的功能，并在FPGA板上成功的实现图形图像的显示，达到了预定的设计目标。

关键词: 嵌入式微处理器, 图形加速芯片, 现场可编程门阵列

ZHAO Jun,ZHANG Ke-huan,LI Ren-fa. Research and design of embedded general image enhancement chip[J]. Computer Engineering and Applications, 2008, 44(26): 74-76.

赵俊,张克环,李仁发. 嵌入式通用图形加速芯片的研究与设计[J]. 计算机工程与应用, 2008, 44(26): 74-76.

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Research and design of embedded general image enhancement chip

嵌入式通用图形加速芯片的研究与设计

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