Computer Engineering and Applications ›› 2009, Vol. 45 ›› Issue (11): 77-81.DOI: 10.3778/j.issn.1002-8331.2009.11.023

• 研发、设计、测试 • Previous Articles     Next Articles

High-throughput LDPC decoder VLSI design for DMB-T

WANG Peng,CHEN Yong-en   

  1. Communication Software & ASIC Design Center,Tongji University,Shanghai 200092,China
  • Received:2008-02-25 Revised:2008-05-06 Online:2009-04-11 Published:2009-04-11
  • Contact: WANG Peng

数字电视标准DMB-T高速LDPC译码器VLSI设计

王 鹏,陈咏恩   

  1. 同济大学 通信软件及专用集成电路设计中心,上海 200092
  • 通讯作者: 王 鹏

Abstract: In chinese national standard for Digital Multimedia Terrestrial Broadcasting(DMB-T),QC irregular LDPC code is used as forward error correction coding.In this paper, according to LDPC distribution property of DMB-T,based on modified Mini-SPA algorithm,a semi-parallel real-time LDPC decoder is presented.Hardware structure is specially optimized for 3 different code rates.Compared with others scheme,RAM block number can be decreased by half,so that global routing is simplified greatly.Whole design is synthesized on Stratix II FPGA.When performing maxmum 20 iterations,decoder throughout can achieve data rate up to 100 Mb/s.

Key words: Low Density Parity Code(LDPC), Digital Multimedia Terrestrial Broadcasting(DMB-T), modified mini-SPA, semi-parallel decoder

摘要: 在我国的数字电视广播地面传输标准DMB-T中,使用了准循环非规则LDPC码作为前向纠错编码。针对此标准中LDPC码的特点,采用修正最小和译码算法,设计了一种半并行结构实时译码器,可实现DMB-T中三种不同码率下的LDPC译码,并有效地实现了硬件结构复用。与其他设计方案相比较,减少了RAM块的数量一半以上,全局布线难度也大大降低。整个设计在Stratix II FPGA上进行了综合验证。当译码迭代次数为20次时,系统吞吐量可达100 Mb/s以上。

关键词: 低密度奇偶校验码, 数字电视广播地面传输标准, 修正最小和算法, 半并行译码器