关键词: 脉冲神经网络, 事件驱动, 抑制型网络, 近似计算, 硬件加速器

Abstract: The design of existing spiking neural network accelerators pays too much attention to the functional integrity of the hardware level and lacks relevant collaborative optimization at the algorithm level to ensure hardware computing efficiency. In addition, traditional event-driven spiking neural network accelerators do not consider the ubiquitous spike jitter phenomenon in spiking neuron models, so they cannot support inhibitory spiking neural networks. In order to solve the above problems, a design method of a suppressive spiking neural network accelerator is proposed by combining software and hardware. At the software optimization level, through the analysis of the calculation redundancy of the spiking neural network, a corresponding approximate calculation method is proposed to reduce the calculation amount of the spiking neural network greatly; at the hardware design level, a calculation module to solve the problem of pulse jitter is proposed, and on this basis, a parallel computing structure suitable for the approximate computing method is designed. In order to verify the rationality of the design, the accelerator prototype FEAS is deployed on Xilinx ZC706 FPGA. The test results on mainstream datasets show that compared with the previous accelerator deployment of spiking neural networks, FEAS has achieved more than an order of magnitude performance improvement while maintaining 97.54% of the original model accuracy.

Key words: spiking neural network, event-driven, inhibitory neural network, approximation calculation, hardware accelerator