关键词: 卷积神经网络（CNN）, 现场可编程逻辑门阵列（FPGA）, 高层综合语言, IP核, 时分复用

Abstract:

In recent years, more and more people choose Field Programmable Gate Array（FPGA） for the implementation of neural network algorithms. The current implementation is mainly based on Verilog Hardware Description Language（Verilog HDL） and High Level Synthesis（HLS）. HLS is easy to understand and use, and its development time is fast. Therefore, this paper uses HLS to design the convolutional layer and pooling layer in the CNN neural network. After generating the IP core, the entire system can be built using time division multiplexing technology. In the experiment, the MNIST data set is used for verification. When the CNN neural network with 10-layers is deployed on the FPGA, the average accuracy is 95.34% after 10,000 iterations. The design of the IP core is of great significance for implementing neural networks with FPGA in short time.

Key words: Convolutional Neural Network（CNN）, Field Programmable Gate Array（FPGA）, high-level integrated language, IP core, time-division multiplexing