关键词: 大数乘法, 串并混合结构, 多次迭代, 现场可编程门阵列

Abstract: This paper proposes an improved algorithm of carry-save large numbers multiplication on FPGA, which can complete multiple iterations of operation in a clock with a serial-parallel hybrid structure. To some extent, reducing clocks to complete a operation, the structure improves the speed of the large numbers multiplication effectively. Finally, the results of the implementation of this multiplier for several operands sizes（192 bit, 256 bit, 384 bit） on Altera Stratix II EP2S90F1508C3 show that the time of 192 bit is 0.185 microsecond , 256 bit is 0.271 microsecond, and 384 bit is 0.595 microsecond. As a result, the paper’s design is about 3.5 times than the previous design in speed.

Key words: large numbers multiplication, serial-parallel hybrid structure, multiple iterations, Field Programmable Gate Array（FPGA）