关键词: 现场可编程门阵列（FPGA）, 全数字锁相环, 自适应, 开关电容滤波, 低通滤波器

Abstract: This paper presents the structure and implementation of an adaptive low-pass filter system based on ADPLL（All Digital Phase Locked Loop）. The input signal is converted into square signal after shaping. The square signal is phase-
locked and transformed into synchronous frequency multiplication signal after passing through the ADPLL based on FPGA. The frequency multiplication signal is input into switched-capacitor filter MAX295 as clk which can control corner frequency. The cutoff frequency of the low-pass filter is tracked automatically with the change of signal frequency. The design principle is introduced. The design method of ADPLL and phase-locked frequency multiplier based on FPGA is analyzed in detail. The experiment results illustrate that the system is feasible and effective. The system is able to realize the self-tracking of double-frequency and filtering when the frequency varies from 1 kHz to 50 kHz.

Key words: Field-Programmable Gate Array（FPGA）, All Digital Phase Locked Loop（ADPLL）, adaptive, switched-capacitor filter, low pass filter