关键词: JPEG2000, 位平面编码, Verilog HDL

Abstract: This paper proposes a new simple and flexible architecture for JPEG2000 bit-plane coding，the architecture contains three state machines to control the coding process.By using local optimization and template technology for data buffering，the coding efficiency is improved.The new architecture has fewer hardware consumption and great flexibility in handling the code block.The Verilog HDL modules of architecture are designed，simulated and synthesized to FPGA，the results show that the architecture designed is correct and the highest frequency of the design is up to 82 MHz.

Key words: JPEG2000, bit-plane coding, Verilog HDL