关键词: 图形流水线, 嵌入式图形, 像素处理

Abstract: Considering the large quantities of data processing and memory access in pixel processing back-end of 3D graphics pipeline，as well as the strict resources and power consumption of embedded system，the paper presents a design of pixel processing back-end hardware.First，the design implements all the test function to ensure various effects；and second it adopts the idea of screen-split rendering，thus reduces the memory requirement；and thirdly it absorbs Early Z algorithm，which can help to abandon sightless triangular surfaces as soon as possible and reduce data amount；finally it realizes the Flip Quad anti-aliasing algorithm and improves image quality.All the RTL modules have been completed and verified on FPGA board.

Key words: graphics pipeline, embedded graphics, pixel processing