关键词: 片上系统, 延迟测试, 测试覆盖率

Abstract: With the increasing enhancement of chip indensity and progress of manufacture technology，new test methodologies and fault models need to be developed to meet the target of high test coverage and product yield.Scan-based at speed test is widely used in deep sub-micro SoC chip delay test.Through successful application of delay test for a high performance，complex mix-signal SoC chip，this paper describes the logic implementation of re-useable clock generation for delay test，delay test pattern generated by ATPG tool.High transition delay and path delay test coverage are achieved with low test cost，meet the requirement of fast time-to-market.

Key words: SoC, delay test, test coverage