关键词: 高速缓冲存储器, 一级Cache, 二级Cache, Cache一致性

Abstract: The Aviation Microelectronic Center of NPU (Northwestern Polytechnical University ) has recently completed the development of a 32-bit super-scalar RISC microprocessor , which we call “Longtium” R2. In this paper we present the design of the Cache of “Longtium” R2, which we deem to be successful because it helps “Longtium” R2 to meet performance requirements. Section 1 shows the architecture of the “Longtium” R2. Fig. 1 gives the schematical diagram of the architecture of the “Longtium” R2. Section 2 discusses in detail L1 Cache. Fig. 2 explains the architecture of L1 instruction Cache. the key desing of L2 Cache is introduced in detail in section 3 ;Section 4 analyzes the Cache Coherent. Simulation and synthesis results are explained in section 5. Section 6 introduces the “Longtium”R2 CPU is fabricated in a 0.18um CMOS process. the die size of the chip is 4.1 mm×4.1 mm and the CPU operating frequency is at least 233MHz .

Key words: RISC, Cache, Cache Coherent