关键词: Benes网络, 重排求解算法, 并行化, 硬件加速器, FPGA

Abstract: Optical interconnect networks use optical cross-connects (OXC) to enable optical switching. Large-scale fast optical cross-connects tend to apply a compact Benes network to avoid high link loss brought by concatenating too many optical switching points. However, Benes network also brings heavy latency overhead for calculating corresponding statuses of its internal switch points to satisfy given route requests, which usually takes hundreds of nanoseconds to microseconds, thus causing a performance bottleneck. This paper proposes a route-solving algorithm of Benes network to decrease such overhead. The algorithm is designed for high-performance hardware implementation. It re-orders the solving procedure to achieve a higher degree of parallelism, and higher working frequency is guaranteed by its simple design. The FPGA-version of the algorithm only uses 26 ns to solve a route-resolving problem of a 16×16 Benes network. With optimized pipeline, its route-solving throughput is increased to 700 MOPs. The route-resolving speed is 9.85 times faster than other FPGA-versions based on the same kind of algorithm, and the route-resolving throughput is 2.8 times bigger. If ASIC technique is applied to build the accelerator chip instead of FPGA, route-resolving time will match the reconfigure latency of high-speed OXC, thus eliminating the performance bottleneck.

Key words: Benes network, permutation algorithm, parallelization, hardware accelerator, FPGA