基于混合架构的卷积神经网络算法加速研究

doi:10.3778/j.issn.1002-8331.2103-0153

摘要/Abstract

摘要： 具有优越性能的卷积神经网络算法已得到广泛应用，但其参数量大、计算复杂、层间独立性高等特点也使其难以高效地部署在较低功耗和较少资源的边缘场景。为此结合该种算法的特点提出了一种基于混合架构的卷积神经网络计算加速方法，该方法选用CPU加FPGA的混合架构，对网络模型进行了压缩优化；在FPGA上通过指令控制数据流的DSP阵列结构实现了卷积计算加速；通过YOLO算法测试了该方法的加速性能，在7 000万门级FPGA上各类资源消耗低于50%且总功耗为7.36 W的情况下，吞吐率达到了120 GOPS。

关键词: 现场可编程门阵列（FPGA）, 卷积神经网络, DSP脉冲阵列

Abstract: Convolutional neural network algorithms with superior performance have a wide range of application, but their large parameters, complex calculations, and high inter-layer independence make it difficult to efficiently deploy in edge scenarios with lower power consumption and fewer resources. For this reason, this article combines the characteristics of this algorithm and proposes a convolutional neural network computing acceleration method based on a hybrid architecture. This method uses a hybrid architecture of CPU and FPGA. The network model is compressed and optimized. Instructions are passed on the FPGA. The DSP array structure that controls the data flow realizes the acceleration of the convolution calculation. The acceleration performance of the method is tested through the YOLO algorithm. The consumption of various resources on the 70 million gate-level FPGA is less than 50% and the total power consumption is 7.36 W. In this case, the throughput rate reaches 120 GOPS.

Key words: field programmable gate array（FPGA）, convolutional neural network（CNN）, digital signal process（DSP） pulse array

郭子博, 高瑛珂, 胡航天, 弓铎, 刘凯, 吴宪云. 基于混合架构的卷积神经网络算法加速研究[J]. 计算机工程与应用, 2022, 58(6): 88-94.

GUO Zibo, GAO Yingke, HU Hangtian, GONG Duo, LIU Kai, WU Xianyun. Research on Acceleration of Convolutional Neural Network Algorithm Based on Hybrid Architecture[J]. Computer Engineering and Applications, 2022, 58(6): 88-94.

参考文献

[1] SZEGEDY C，LIU W，JIA Y Q，et al.Going deeper with convolutions[C]//2015 IEEE Conference on Computer Vision and Pattern Recognition（CVPR），Boston，2015.USA：IEEE，2015：1-9.
[2] LECUN Y，BENGIO Y，HINTON G.Deep learning[J].Nature，2015，521（7553）：436-444.
[3] KRIZHEVSKY A.ImageNet classification with deep convolutional neural networks[J].Communications of the ACM，2017，60（6）：84-90.
[4] HAN S，MAO H，DALLY W J.Deep compression：compressing deep neural networks with pruning，trained quantization and huffman coding[J].arXiv：1510.00149，2015.
[5] SANDLER M，HOWARD A，ZHU M，et al.Mobilenetv2：inverted residuals and linear bottlenecks[C]//Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition（CVPR），Salt Lake City，2018.USA：IEEE，2018：4510-4520.
[6] ZHANG X，ZHOU X，LIN M，et al.Shufflenet：an extremely efficient convolutional neural network for mobile devices[C]//Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition（CVPR），Salt Lake City，2018.USA：IEEE，2018：6848-6856.
[7] 谢阳杰.基于FPGA加速器的SSD目标检测技术研究与实现[D].西安：西安电子科技大学，2019.
XIE Y J.Research and implementation of SSD target detection technology based on FPGA accelerator[D].Xi’an：Xidian University，2019.
[8] CHEN T，DU Z，SUN N，et al.Diannao：a small-footprint high-throughput accelerator for ubiquitous machine-learning[J].ACM SIGARCH Computer Architecture News，2014，42（1）：269-284.
[9] CHEN Y H，YANG T J，EMER J，et al.Eyeriss v2：a flexible accelerator for emerging deep neural networks on mobile devices[J].IEEE Journal on Emerging and Selected Topics in Circuits and Systems，2019，9（2）：292-308.
[10] JOUPPI N P，YOUNG C，PATIL N，et al.In-datacenter performance analysis of a tensor processing unit[C]//Proceedings of the 44th Annual International Symposium on Computer Architecture（ISCA），Toronto 2017.New York：ACM，2017：1-12.
[11] NAKAHARA H，YONEKAWA H，FUJII T，et al.A lightweight yolov2：a binarized cnn with a parallel support vector regression for an fpga[C]//Proceedings of the 2018 ACM/SIGDA International Symposium on field-programmable gate arrays，Monterey，2018.New York：ACM，2018：31-40.
[12] DING C，WANG S，LIU N，et al.REQ-YOLO：a resource-aware，efficient quantization framework for object detection on FPGAs[C]//Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays，Seaside，2019.New York：ACM，2019：33-42.
[13] 吕灵玥.针对SSD-ResNet的神经网络压缩研究[D].西安：西安电子科技大学，2019.
LV L Y.Research on neural network compression for SSD-ResNet[D].Xi’an：Xidian University，2019.
[14] 胡航天，刘凯，马士超，等.专用指令集在基于FPGA的神经网络加速器中的应用[J].空间控制技术与应用，2020，46（3）：36-41.
HU H T，LIU K，MA S C，et al.Application of special command set in neural network accelerator based on FPGA[J].Aerospace Control and Application，2020，46（3）：36-41.
[15] 王奥博.基于FPGA平台的YOLOv3算法体系结构的研究[D].西安：西安电子科技大学，2020.
WANG A B.Research on YOLOv3 algorithm architecture based on FPGA platform[D].Xi’an：Xidian University，2020.
[16] REDMON J，FARHADI A，REDMON J.Yolov3：an incremental improvement[J].arXiv：1804.02767，2018.
[17] SHEN J，HUANG Y，WANG Z，et al.Towards a uniform template-based architecture for accelerating 2D and 3D CNNs on FPGA[C]//Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays，Monterey，2018.New York：ACM，2018：97-106.
[18] PREUSSER T B，GAMBARDELLA G，FRASER N，et al.Inference of quantized neural networks on heterogeneous all-programmable devices[C]//2018 Design，Automation & Test in Europe Conference & Exhibition（DATE），Paris，2018.USA：IEEE，2018：833-838.