Abstract: Turbo encoding with frame splitting and trellis zero termination provides a suitable structure for implementing the segmented-based parallel Turbo decoding.The performance simulation，together with the FPGA design and implementation of the proposed Turbo coding scheme unveils that，the overlapping between neighboring segments to guarantee the achieved reliability can be saved，which may be helpful to achieve higher decoding throughput especially for short block size cases.Secondly，the frame splitting with trellis zero termination encoding process implies that both the initial and the end states of each segment are specified with the known all-zeros state，and this may make the SISO decoder respecting to each sub-block independent from each other，which may give rise to a simplified FPGA design.Finally，the segment based trellis zero termination structure property is favorable for a faster convergence in iterative decoding.