关键词: 现场可编程门阵列（FPGA）, 亚稳态, 格雷码, 高速FIFO

Abstract: To overcome the metastability and ensure the validation of data transfer，the asynchronous First In First Out（FIFO） modules are often used to buffer data in systems with data transfers crossing clock domains.Because of the existence of the addressing pointers，which often adopt Gray-code counters，and the“full & empty” generation logic in a usual asynchronous FIFO module，the signals passing two modules may suffer large delay.As a result，the working frequency of the whole module is limited.Based on a premise that the“full” state will never occur in a high-frequency system，a method of implementing high speed asynchronous FIFO in FPGA is proposed.The focus on this way is that the “full” flag generation logic and redundant RAM depth are omitted，i.e.，only the“empty” flag is generated.So，the design of FIFO is simplified.The results from simulation and synthesis design show that the working speed of the whole module is greatly increased.

Key words: Field-Programmable Gate Array（FPGA）, metastability, gray-code, high-speed FIFO