关键词: 伪双口随机存储器（TP RAM）, 单口随机存储器（SP RAM）, 接口转换逻辑, 自适应门控时钟, 格雷码

Abstract: As the area and power consumption of TP RAM in SoC are large, a new design method of optimization is proposed. In order to achieve the function of the original TP RAM and keep the external interface unchanged, TP RAM is replaced with SP RAM, and read-write interface logics of conversion are added around SP RAM. For less power, adaptive clock-gating is used and address bus is encoded through Gray code. The method discussed in this paper is used in the multi core SoC chip which has been successfully taped out in TSMC 28 nm HPC process. The chip occupies 10.5 mm×11.3 mm of die area and consumes 17.07 W. The testing results indicate that the area of optimized RAMs is reduced by 25.2%, and the power saving is 43.07%.

Key words: Two Ports Random Access Memory（TP RAM）, Single Port Random Access Memory（SP RAM）, interface logics of conversion, adaptive clock-gating, Gray code