计算机工程与应用 ›› 2009, Vol. 45 ›› Issue (10): 69-71.DOI: 10.3778/j.issn.1002-8331.2009.10.021

• 研发、设计、测试 • 上一篇    下一篇

多核多线程处理器二级Cache预取结构的设计

杨 可,樊晓桠,王党辉   

  1. 西北工业大学 航空微电子中心,西安 710072
  • 收稿日期:2008-09-19 修回日期:2008-12-02 出版日期:2009-04-01 发布日期:2009-04-01
  • 通讯作者: 杨 可

Prefetch structure of L2 Cache for multi-core multi-thread pocessor

YANG Ke,FAN Xiao-ya,WANG Dang-hui   

  1. Aviation Microelectronic Center,Northwestern Polytechnical University,Xi’an 710072,China
  • Received:2008-09-19 Revised:2008-12-02 Online:2009-04-01 Published:2009-04-01
  • Contact: YANG Ke

摘要: 合理的设计二级Cache是有效地减少多核多线程处理器存储器访问延迟的方法。针对现有的多核多线程处理器,讨论了二级Cache的混合预取结构设计方案。通过详细设计和仿真分析,结果表明混合预取结构可有效提高处理器的整体性能。特别是采用不命中混合预取结构的二级Cache性能更佳,适合满足此类结构的多核多线程处理器需求。

Abstract: The effective way of reducing memory accessing delay of the multi-core multi-thread processor is to design L2 Cache reasonable.This paper aims at the present multi-core multi-thread processor, then discusses the design project of mixed-prefetch structure of L2 Cache.By particular design and simulation analyses,it indicates that mixed-prefetch structure can improve the performance of processor remarkably.Furthermore, mixed-prefetch structure with prefetch under miss strategy suits the multi-core multi-thread processor much better,which meets the requirement of the multi-core multi-thread processor with this structure.