3D堆叠芯片硅通孔容错设计

计算机工程与应用 ›› 2015, Vol. 51 ›› Issue (14): 11-16.

3D堆叠芯片硅通孔容错设计

张玲1，王伟征2，梅军进1

1.湖北理工学院计算机学院，湖北黄石 435003
2.长沙理工大学　计算机与通信工程学院，长沙 410004

出版日期:2015-07-15 发布日期:2015-08-03

Fault-tolerant design for TSVs of 3D stacked ICs

ZHANG Ling1, WANG Weizheng2, MEI Junjin1

1.School of Computer, Hubei Polytechnic University, Huangshi, Hubei 435003, China
2.School of Computer & Communication Engineering, Changsha University of Science & Technology, Changsha 410004, China

Online:2015-07-15 Published:2015-08-03

摘要/Abstract

摘要： 3D堆叠芯片采用硅通孔（Through-Silicon Vias，TSVs）技术垂直连接多个裸晶（die），具有较高的芯片性能和较低的互连损耗，引起工业界和学术界的广泛关注。随着3D芯片堆叠层数的增加，一个TSV小故障都可能导致成本的大幅度增加和芯片良率的大幅度降低。TSV的密度与故障的发生概率有着密切的关系，TSV密度较大时，其发生故障的概率就会增大。为了减少故障产生的概率，提高良率，提出一种以密度为导向的TSV容错结构，首先将TSV平面分成多个密度区间，密度较大区间的信号TSV被分配较多的修复TSV，但同时此区间上设计尽量少的修复TSV，以减少此区间内总的TSV密度。理论分析和实验结果均表明该方法可以有效地减少故障发生的概率，并对故障TSV进行修补，同时具有较小的硬件代价。

关键词: 3D堆叠芯片, 硅通孔, 容错技术

Abstract: 3-D technology that uses Through Silicon Via（TSV） providing communication links for dies in vertical direction provides many benefits including high density, low power, and small form-factor. It has drawn public attention at the industry and academia. With the number of stacked dies increasing , a failed TSV may increase the cost and decrease the yield severely. A TSV fault-tolerant architecture is proposed in the paper. The chip is divided into several density region first, then the repair TSVs are allotted according the density region’s density, the larger the density, the more repair TSVs are allotted, which not only reduce the number of repair TSVs, the density of the all TST could be redistribution. The hardware and the repair rate are also analyzed in the paper, which show the proposed scheme could recover most of the failed chips with reasonable cost. The experimental results also prove the efficiency of the proposed scheme.

Key words: 3D stacked chip, Through Silicon Via（TSV）, fault-tolerant design

张玲1，王伟征2，梅军进1. 3D堆叠芯片硅通孔容错设计[J]. 计算机工程与应用, 2015, 51(14): 11-16.

ZHANG Ling1, WANG Weizheng2, MEI Junjin1. Fault-tolerant design for TSVs of 3D stacked ICs[J]. Computer Engineering and Applications, 2015, 51(14): 11-16.

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