计算机工程与应用 ›› 2011, Vol. 47 ›› Issue (35): 84-87.

• 研发、设计、测试 • 上一篇    下一篇

一种FPGA抗辐射布线算法设计

陈 丽,缪 斯,杨文龙,王伶俐   

  1. 复旦大学 专用集成电路与系统国家重点实验室,上海 201203
  • 收稿日期:1900-01-01 修回日期:1900-01-01 出版日期:2011-12-11 发布日期:2011-12-11

Radiation-tolerant routing algorithm design for FPGAs

CHEN Li,MIAO Si,YANG Wenlong,WANG Lingli   

  1. State Key Lab of Application Specific Integrated Circuit & System,Fudan University,Shanghai 201203,China
  • Received:1900-01-01 Revised:1900-01-01 Online:2011-12-11 Published:2011-12-11

摘要: 随着集成密度的增大以及工作电压的降低,基于SRAM的FPGA芯片更加容易受到单粒子翻转的影响。提出了一种基于通用布局布线工具VPR的抗辐射布线算法,通过改变相关布线资源节点的成本函数,来减少因单粒子翻转引起的桥接错误,并与VPR比较下板测试结果。实验结果表明,该布线算法可以使芯片的容错性能提升20%左右,并且不需要增加额外的硬件资源或引入电路冗余。

关键词: SRAM型现场可编程门阵列, 单粒子翻转, 通用布局布线算法, 布线

Abstract: With higher density and lower operating voltage,SRAM-based Field Programmable Gate Arrays(FPGAs) are more sensitive to Single Event Upset(SEU).A VPR-based anti-SEU algorithm is presented,by modifying relative routing resources’ cost function to minimize bridging errors caused by SEU.The experimental results show that this method can improve FPGA chip’s soft-error tolerance performance by 20% compared with VPR,without introducing extra hardware resources and additional design redundancy.

Key words: SRAM-based Field Programmable Gate Arrays(FPGA), Single Event Upset(SEU), Versatile Placement and Routing(VPR), routing