关键词: 扫描链, 测试功耗, 选择触发, 差分向量

Abstract: This paper presents a new selective trigger scan chain architecture by changing traditional scan design using a scan register，whose length is equal to that of scan chain.It can efficiently reduce dynamic power in shift cycle and increase the scan clock frequency.The test data that the architecture requires is difference test vector set，so a separate CSR（Cyclical Scan Register） isn’t required in decompression after encoding lengths of runs of 0s in the test data.Experiment results on ISCAS’89 benchmark circuits show that the proposed technique is more superior to reduce average power during scan test than traditional scan design.

Key words: scan chain, test power, selective trigger, difference vector