支持AltiVec技术的可分裂式加法器研究与设计

doi:10.3778/j.issn.1002-8331.2009.12.021

计算机工程与应用 ›› 2009, Vol. 45 ›› Issue (12): 63-65.DOI: 10.3778/j.issn.1002-8331.2009.12.021

支持AltiVec技术的可分裂式加法器研究与设计

黄小平,樊晓桠,张盛兵,庄伟

西北工业大学计算机学院，西安 710072

收稿日期:2008-02-25 修回日期:2008-03-27 出版日期:2009-04-21 发布日期:2009-04-21
通讯作者: 黄小平

Research and design of fissile adder for AltiVec technology

HUANG Xiao-ping,FAN Xiao-ya,ZHANG Sheng-bing,ZHUANG Wei

School of Computer，Northwestern Polytechnical University，Xi’an 710072，China

Received:2008-02-25 Revised:2008-03-27 Online:2009-04-21 Published:2009-04-21
Contact: HUANG Xiao-ping

摘要/Abstract

摘要： AltiVec技术是PowerPC体系结构处理器采用的多媒体向量处理技术。研究和设计了支持该技术的128位可分裂式加法器。该加法器可分裂实现16个字节、8个半字、4个字的并行加法操作。从时序、面积以及验证的复杂度等方面对三种设计方法进行了分析比较。

关键词: AltiVec技术, 加法器, 可分裂, 先行进位

Abstract: AltiVec is a vector processing technology adopted by PowerPC processor.A fissile adder for it is presented.The 128-bits fissile adder can finish sixteen bytes add-operations or eight half-words add-operations or four words add-operations.It also provides the analysis of the timing，area and the verification complexity as to different design methods.

Key words: AltiVec technology, adder, fissile, carry-look ahead

黄小平,樊晓桠,张盛兵,庄伟. 支持AltiVec技术的可分裂式加法器研究与设计[J]. 计算机工程与应用, 2009, 45(12): 63-65.

HUANG Xiao-ping,FAN Xiao-ya,ZHANG Sheng-bing,ZHUANG Wei. Research and design of fissile adder for AltiVec technology[J]. Computer Engineering and Applications, 2009, 45(12): 63-65.

支持AltiVec技术的可分裂式加法器研究与设计

Research and design of fissile adder for AltiVec technology

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