低功耗并行的二维离散小波变换的VLSI结构

计算机工程与应用 ›› 2008, Vol. 44 ›› Issue (18): 73-75.

低功耗并行的二维离散小波变换的VLSI结构

刘鸿瑾^1,2,何星^1,2,张铁军¹,王东辉¹,于其英³,侯朝焕¹

1.中国科学院声学所，北京 100080
2.中国科学院研究生院，北京 100039
3.山东省昌邑市奎聚中学，山东昌邑 261300

收稿日期:2007-09-18 修回日期:2008-01-09 出版日期:2008-06-21 发布日期:2008-06-21
通讯作者: 刘鸿瑾

Low power parallel VLSI architecture for 2-D discrete wavelet transform

LIU Hong-jin^1,2,HE Xing^1,2,ZHANG Tie-jun¹,WANG Dong-hui¹,YU Qi-ying³,HOU Chao-huan¹

1.Institute of Acoustics，Chinese Academy of Sciences，Beijing 100080，China
2.Graduate University of Chinese Academy of Sciences，Beijing 100039，China
3.Kuiju High School of Shandong Province，Changyi，Shandong 261300，China

Received:2007-09-18 Revised:2008-01-09 Online:2008-06-21 Published:2008-06-21
Contact: LIU Hong-jin

摘要/Abstract

摘要： 提出了一种基于提升算法的低功耗并行的二维离散小波变换的VLSI结构。提出结构的同时进行行和列方向的处理，不需要额外的缓存来存储用于列变换的中间变换系数。通过分时复用关键的运算功能模块，该结构同时可以对两行数据进行处理，硬件的利用率达到100%。边界对称扩展通过嵌入式电路实现，大大降低了需要的片上存储器的数量以及对片外存储器的访问，有效地降低了系统的功耗。

Abstract: A highly efficient VLSI architecture for the （9/7） 2-D DWT based on a lifting scheme is presented.The proposed architecture processes the row and column transforms simultaneously，eliminates the memory buffer for the column transform coefficients.The hardware utilization is speeded up to 100% by processing two independent data streams together using shared arithmetic functional blocks.And the embedded boundary extension circuit is exploited to optimize the architecture.Compared to previous architectures，the proposed architecture has more efficiency on critical path，power consumption，temporal storage usage and hardware utilization.

刘鸿瑾^1,2,何星^1,2,张铁军¹,王东辉¹,于其英³,侯朝焕¹. 低功耗并行的二维离散小波变换的VLSI结构[J]. 计算机工程与应用, 2008, 44(18): 73-75.

LIU Hong-jin^1,2,HE Xing^1,2,ZHANG Tie-jun¹,WANG Dong-hui¹,YU Qi-ying³,HOU Chao-huan¹. Low power parallel VLSI architecture for 2-D discrete wavelet transform[J]. Computer Engineering and Applications, 2008, 44(18): 73-75.