可重配置处理器的体系结构级功耗模型与分析

计算机工程与应用 ›› 2007, Vol. 43 ›› Issue (26): 34-37.

可重配置处理器的体系结构级功耗模型与分析

肖玮,臧斌宇,朱传琪

复旦大学并行处理研究所,上海 200433

收稿日期:1900-01-01 修回日期:1900-01-01 出版日期:2007-09-11 发布日期:2007-09-11
通讯作者: 肖玮

Architecture-level power modeling and analyzing for reconfigurable processor

XIAO Wei,ZANG Bin-yu,ZHU Chuan-qi

Parallel Processing Institute,Fudan University,Shanghai 200433,China

Received:1900-01-01 Revised:1900-01-01 Online:2007-09-11 Published:2007-09-11
Contact: XIAO Wei

摘要/Abstract

摘要： 按照可重配置处理器的体系结构建立并实现功耗模型;模型对处理器的电路级特性进行抽象,基于体系结构级属性和工艺参数进行静态峰值功耗估算,基于性能模拟器进行动态功耗统计,并实现三种条件时钟下的门控技术;可重配置处理器与超标量通用微处理器相比,在性能方面获得的平均加速比为3.59,而在功耗方面的平均增长率仅为1.48;通过实验还说明采用简单的CC1门控技术能有效地降低可重配置系统的功耗和硬件复杂度;该模型为可重配置处理器低功耗设计和编译器级低功耗优化研究奠定了基础。

关键词: 可重配置处理器, 体系结构级功耗模型, 参数化功耗模型, 动态功耗模型, 低功耗优化

Abstract: Power model is presented and implemented according to the architecture of reconfigurable processor.The circuit characteristics of the processor are abstracted.Peak power is estimated based on architecture-level attribute and technology parameters.Dynamic power is computed based on performance simulator and clock gating of three conditional clocking styles is implemented.Compared with superscalar general-purpose microprocessor,reconfigurable processor can gain an average speedup of 3.59 but power is only increased by 1.48 on average.Experiment results also show that simple CC1 clock gating technology can reduce power dissipation and hardware complexity of reconfigurable system effectively.This power model is suitable for low power design and compiler optimization research of reconfigurable processor.

Key words: reconfigurable processor, architecture-level power model, parameterizable power model, dynamic power model, low-power optimization

肖玮,臧斌宇,朱传琪. 可重配置处理器的体系结构级功耗模型与分析[J]. 计算机工程与应用, 2007, 43(26): 34-37.

XIAO Wei,ZANG Bin-yu,ZHU Chuan-qi. Architecture-level power modeling and analyzing for reconfigurable processor[J]. Computer Engineering and Applications, 2007, 43(26): 34-37.