Abstract: A new method of implementing high order FIR filter with FPGA is presented.This method divides high order FIR filter into some lower order FIR filters by using polyphase decomposition structure，and implements the lower order FIR filters with modifying Distributed Arithmetic.A series of FIR filters which orders form 8 to 1，024 is designed.These proposed filters have been simulated and synthesized with Quartus II 7.1，implemented with an EP2S60F1020C4 FPGA device.Results show that the proposed method can implement FIR filters with the smaller resource usage and high speed.