计算机工程与应用 ›› 2010, Vol. 46 ›› Issue (12): 75-78.DOI: 10.3778/j.issn.1002-8331.2010.12.020

• 研发、设计、测试 • 上一篇    下一篇

分布算术并行结构设计研究

梁 刚1,赵 伟2,张洵颖3   

  1. 1.河南大学 计算机与信息工程学院,河南 开封 475004
    2.河南大学 国际教育学院,河南 开封 475001
    3.西安微电子技术研究所,西安 710054
  • 收稿日期:2009-02-17 修回日期:2009-04-20 出版日期:2010-04-21 发布日期:2010-04-21
  • 通讯作者: 梁 刚

Research and design of parallel architecture of distributed arithmetic

LIANG Gang1,ZHAO Wei2,ZHANG Xun-ying3   

  1. 1.Department of Computer and Information Engineering,Henan University,Kaifeng,Henan 475004,China
    2.School of International Education,Henan University,Kaifeng,Henan 475001,China
    3.Xi’an Microelectronics Technology Institute,Xi’an 710054,China
  • Received:2009-02-17 Revised:2009-04-20 Online:2010-04-21 Published:2010-04-21
  • Contact: LIANG Gang

摘要: 提出一种基于DA实现的可扩展的阵列结构,通过对阵列的配置使其具有良好的扩展能力以及并行处理的高效特性。该结构与传统的采用ASIC电路的实现方式相比,较好地解决了ASIC电路中阶数、数据字宽不可自适应调整以及存储量需求较大、吞吐量偏低的问题。最后在实现代价和性能方面与典型结构进行了比较,证明了该结构存储量需求小,运算时间少,具有较好的性价比。

关键词: 分布算术, 并行DA, PE阵列, 前缀求和

Abstract: A kind of scalable array architecture based on DA implementation is proposed.Better scalability and high parallel processing efficiency can be obtained by array configuration.Compared with traditional ASIC implementation,this architecture not only properly solves the problems of disability of self adaptation of order and data word width,but also solves the problem of large storage requirement and low throughput of ASIC.The implementation cost and performance comparison with typical architecture are presented in the last part,which demonstrate that the proposed architecture has lower memory requirements,lower time cost and better performance-cost ratio.

Key words: distributed arithmetic, Parallel DA(PDA), PE array, prefix-accumulation

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