关键词: 同步数据触发结构, 多核处理器, 作废, 同步技术

Abstract: The “busy-wait” technology is often used to implement locks or barriers in shared memory multi-core processors.These synchronization mechanisms are restricted by the long latency and resource contention problems and are not scalable.They often need to access memory repeatedly and affect the normal memory accessing process.A synchronization technology based on the invalidation of instruction cache for the SDTA-based multi-core processor is proposed.At the synchronization point，the processor cores invalidate the corresponding instruction cachelines which cause instruction fetch miss.Then instruction fetch requests are issued to the L2 cache.The L2 cache adopts a filter mechanism to freeze those fetch requests to suspend the processor cores that need synchronization.The proposed mechanism is scalable and has a better performance.

Key words: Synchronous Data Triggered Architecture（SDTA）, multi-core processor, invalidation, synchronization