关键词: 超长指令字, 缓存重构, 可重构缓存, 发射宽度

Abstract: Dynamically reconfigurable cache has a significant advantage in the scope of resource utilization and power consumption due to the reconfiguration of cache capacity, structure, mapping rules at run-time. In view of the characteristics of the dynamic issue-width of the VLIW processor, this paper uses its dynamic features to drive the resizing cache during run-time. In such a manner, the data path can be allocated well so as to split and merge cores dynamically. This is different from the traditional approaches that monitor the cache’s miss rate. To further smoothen the performance of reconfigurable cache in the frequent scenario, a novel, and simple cache strategy is proposed. Thus, it ensures a smooth cache performance from one cache size to the other. The simulation results show that the method can achieve an average decrease of 16% during the 2 000 cycles after cache reconfiguration occurs, and the whole performance is improved.

Key words: Very Long Instruction Word（VLIW）, cache resizing, reconfiguration cache, issue-width