关键词: 三维片上系统（3D SoC）, 测试访问机制（TAM）, 测试外壳, 测试调度, 测试时间

Abstract:

An optimized strategy is proposed for 3D System on Chip（SoC） parallel testing in the mid-bond test phase under power and multi-core test parallelism constraints. By reasonably allocating Test Access Mechanism（TAM）, test time is greatly reduced and test cost is also reduced. In the testing process of 3D SoC, the TAM resource of the chip is very limited. The method of this paper makes the core of each layer in test schedule in order by the number of testing TAM resources occupied. By designing the corresponding test wrapper structure, the idle TAM resources under the current state of the system and the internal scan chains of cores under test are redistributed, in order to make cores waiting for scheduling advance into test phase, and reduce idle time in parallel testing. On the basis of the structure, the scheduling sequence of each core is adjusted to make the test process meet all constraints. Experimental results show that compared with traditional methods, the method proposed in this paper reduces the test time more effectively.

Key words: 3D System on Chip（3D SoC）, Test Access Mechanism（TAM）, test wrapper, test scheduling, test time