关键词: 按序退休, 重排序缓存, 快速退休, 乱序回写

Abstract: In high-performance superscalar microprocessors, when long latency instructions reach the top of reorder buffer, instructions in the pipeline retire slowly. In this paper, a highly efficient retirement architecture is proposed, in which instructions can fast retire as soon as they are confirmed without exception and mis-prediction. Then results can be written back out of order. A result buffer is seperated from reorder buffer to achieve register renaming and out-of-order writing back. Reorder buffer is in charge of instructions’s in-order retirement and maintance of the precise exception. When the reorder buffer confirms that an instruction will not generate exception, this instruction fast retires from the reorder buffer and waits for the result in the result buffer. The experiment shows that in the condition of the same resource, the performance can be increased by 33% compared to the traditional architecture.

Key words: in-order retirement, Reorder Buffer（ROB）, fast retire, out-of-order write back