关键词: 超大规模集成电路（VLSI）, 可测性, 敏化方程, 时序泰勒展开图

Abstract: This paper proposes a VLSI high-level testability analysis（TA） new approach HLTA-TTED based on Timed Taylor Expansion Diagram（TTED），which models the critical sensitization path with TTED and establishes a unique representation model of certainty and probability failure.The line’s sensitization is obtained by using the symbolic variable.Considering the case of single sensitization and multi-sensitization of the circuit，this paper computes and analyzes the testability of the circuit.A good result is obtained at last，the experiment confirms the approach’s effectiveness.

Key words: Very Large Scale Integrated circuits（VLSI）, testability, sensitization equation, Timed Taylor Expansion Diagram（TTED）