关键词: 浮点乘加器, 多通道, 低功耗

Abstract: The multiply-add operation is becoming important increasingly with the development of application specific microprocessor oriented to DSP and some other interrelated fields. The computation of a multiplication and the summation of the result with another operand can be performed concurrently reducing, in this way, the latency of the overall operation. Based on the idea of multi-path, this thesis proposes an improved multi-path floating-point fused multiply-add (MAF). The process is divided into four data paths according to the relative position of operand A from the result of B×C. Each path uses the separate operation process so that the unwanted delay is avoided. By contrast, we can conclude that the multi-path MAF architecture has advantages in both the speed and the power.

Key words: loating-point fused multiply-add, multi-path, low power