关键词: 子字并行, 乘法器, 多媒体

Abstract: This paper proposes a multiplier architecture capable of supporting subword parallelism，and has completed its VLSI design and implementation using 0.18 μm standard cell process.Based on the 16 bit array sub-word parallel architecture，this multiplier extends signed and unsigned hybrid operations，and uses multi-cycle combination technique to realize 32 bit sub-word parallel operations.In addition，it also supports sub-word multiply accumulate operations.With pipelined operation style，it can perform one 32×16，two 16×16，and four 8×8 bit signed/unsigned multiplications in single cycle respectively.The implementation results show that the proposed sub-word parallel multiplier can reduce the area and improve the frequency，which is a good compromise of hardware consumption and performance.It is well suitable for multimedia microprocessor design.

Key words: subword parallelism, multiplier, multimedia