Abstract: A fast parallelable multiplier architecture over GF（2^m） is presented based on the reconfigurable most significant bit serial multiplier.One control signal and six two-way muxes are added in the multiplier，and it can use the fixed hardware resource to compute two multiplication parallelly，when the field length is less than half of the maximum.The proposed multiplier architecture has low circuit complexity and low power cost.It can use limited registers to accelerate computing，and also can be applied to the serial-parallel architecture.It suits the VLSI design of reconfigurable cryptographic applications with limited storage and low hardware complexity.