计算机工程与应用 ›› 2009, Vol. 45 ›› Issue (33): 64-66.DOI: 10.3778/j.issn.1002-8331.2009.33.020

• 研发、设计、测试 • 上一篇    下一篇

VLSI平面布图规划中模拟退火算法的加速策略

周晓方,王琳凯,陈珊珊,赵长虹   

  1. 复旦大学 专用集成电路与系统国家重点实验室,上海 201203
  • 收稿日期:2008-09-22 修回日期:2008-12-23 出版日期:2009-11-21 发布日期:2009-11-21
  • 通讯作者: 周晓方

Simulation annealing accelerating in VLSI floorplanning

ZHOU Xiao-fang,WANG Lin-kai,CHEN Shan-shan,ZHAO Chang-hong   

  1. State Key Laboratory of ASIC & System,Fudan University,Shanghai 201203,China
  • Received:2008-09-22 Revised:2008-12-23 Online:2009-11-21 Published:2009-11-21
  • Contact: ZHOU Xiao-fang

摘要: 布局是现代VLSI物理设计中十分关键的步骤,而模拟退火等智能算法在针对宏模块布局的平面布图规划问题中得到广泛应用。针对应用于VLSI平面布图规划的模拟退火算法进行了研究和分析,并针对布图本身特性在退火算法中采用了一种导向性的邻域构造策略来加速算法的收敛,有效地提高了平面布图规划中模拟退火算法的搜索效率。

关键词: 超大规模集成电路(VLSI), 布图规划, 模拟退火, 加速

Abstract: Floorplanning and placement are key steps in modern VLSI physical design,and Simulation Annealing(SA) is widely used in floorplanning algorithms.This paper has research on SA algorithm used in floorplanning and accelerates the convergence rate of the algorithm through designing new neighborhood solution generating strategies in the SA process,and gets better efficiency.

Key words: Very Large Scale Integrated circuites(VLSI), floorplanning, simulation annealing, accelerate

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