%0 Journal Article %A FANG Kanfei %A LIN Zhitin %A ZHAO Jianzhong %A LI Zhi %A BI Liqiang %T Design of New BMC Decoding Circuit for USB PD3.0 Protocol %D 2021 %R 10.3778/j.issn.1002-8331.2003-0210 %J Computer Engineering and Applications %P 77-83 %V 57 %N 1 %X

For the traditional BMC(Biphase Mark Coding) decoding in USB PD3.0(Universal Serial Bus Power Delivery) protocol, it has the disadvantages of high power consumption, large area, and poor interference resistance. A new decoding system with low power consumption, small area and strong robustness with automatic correction function is proposed. This system makes full use of the advantages of FIR(Finite Impulse Response) filtering algorithm and moving average filtering algorithm to make it better serve the decoding system. In addition, the system also adds a signal monitoring function. In order to verify the reliability of the system, the system is described in Verilog language under the DC development platform of Synopsys companies and verified by simulation. Experimental results show that under the same conditions, the system is significantly more robust than traditional decoding circuits, with an area reduction of 2.19% and a power consumption reduction of 2.06%, which fully reflects the low power consumption, small area, and strong anti-interference ability, etc.. This system lays a theoretical foundation for improving the reliability and practicability of USB PD fast charging chip design, and improves the charging efficiency of USB PD3.0.

%U http://cea.ceaj.org/EN/10.3778/j.issn.1002-8331.2003-0210