%0 Journal Article %A TU Feng’e %A XIA Yinshui %A CHU Zhufei %A WANG Lunyao %T Fast gate level dual-voltage assignment algorithm under timing constraints %D 2015 %R %J Computer Engineering and Applications %P 201-205 %V 51 %N 11 %X Against the low speed of gate-level voltage assignment algorithm, a gate grouping based dual-voltage assignment algorithm under timing constraint is proposed. Through comparing gate delay difference working under low and high voltage and its slack, all gates are classified into high voltage gate group and low voltage gate group. Against so-called critical low voltage gates violating timing constraint on critical paths, the min-cut method is employed to gradually increase the applied voltage until the circuit meets timing constraint. The experimental results on ISCAS’85 benchmarks indicate that compared with the published algorithms, the proposed algorithm not only can reduce power dissipation, but also can improve algorithm speed. %U http://cea.ceaj.org/EN/abstract/article_33306.shtml