Abstract: To study the efficiency of generating VLSI test chip, a method which uses a layout editor for drawing and models parameters in batch is proposed. This method can not only shorten design cycle, but also reduce difficulty. A set of test chips for PDK has been implemented by the method, and the final result proves the efficiency.

Key words: Very Large Scale Integrated circuits（VLSI）, test chip, Kelvin structure, Process Design Kit（PDK）, Component Description Format（CDF）

摘要： 对生成测试芯片效率进行研究，提出了一种采用版图编辑器作图和批量参数化建模设计方法。缩短了设计周期，降低了设计难度。依据该方法，开发了一套针对工艺开发包的测试芯片，实验结果验证了其高效性。

关键词: 超大规模集成电路, 测试芯片, 开尔文结构, 工艺开发包, 组件描述格式