Computer Engineering and Applications ›› 2007, Vol. 43 ›› Issue (20): 109-112.

• 产品、研发、测试 • Previous Articles     Next Articles

Design of CAVLC decoder IP core in H.264/AVC standard

AI Ming-jing,ZHANG Zhe,DENG Yuan   

  1. School of Computer Engineering,Beihang University,Beijing 100083,China
  • Received:1900-01-01 Revised:1900-01-01 Online:2007-07-11 Published:2007-07-11
  • Contact: AI Ming-jing

H.264/AVC中CAVLC解码器IP核的设计

艾明晶,张 哲,邓 媛   

  1. 北京航空航天大学 计算机学院,北京 100083
  • 通讯作者: 艾明晶

Abstract: CAVLC is the entropy module of H.264/AVC,which can affect H.264/AVC decoder’s performance directly.Based on existing CAVLC decoder,this paper proposes architecture of CAVLC decoder based on FPGA.This architecture uses the dispersive control strategy to simplify the design,improves some decoder module,and design parallel register array to support the following inverse quantization and inverse transform.After the synthesis in QuatrusII 5.0 of Altera company and timing simulation in ModelSim6.1,this design can fulfill the performance requirement of baseline profile,level 3.0 in H.264 standard.

Key words: H.264, variable decoder, CAVLC, decoder

摘要: CAVLC(Context-Adaptive Variable Length Coding,基于上下文的变长变码)是H.264/AVC的熵解码模块,其性能优劣直接影响H.264/AVC 解码器的性能。在现有的CAVLC解码器基础上,提出了一种基于FPGA的CAVLC解码器的体系结构,采用分散控制的策略,简化了设计,对CAVLC的部分解码模块作了改进,并设计了并行化寄存器组,适于后续快速反量化反变换模块的设计。通过在Altera公司的QuartusII5.0进行综合并在ModelSim6.1下进行时序仿真可知,该设计至少能够满足H.264标准BaseLine档次、级数(Level)3.0的要求。

关键词: H.264, 变长解码, Context-Adaptive Variable Length Coding(CAVLC), 解码器