Abstract: The software efficiency of Elliptic Curve Cryptography（ECC） algorithm over [GF(p)] is analyzed. Against the disadvantages of the software implementation, the partition between software and hardware is given. A kind of hardware accelerator suitable for Sytem-on-Chip（SoC） is proposed, and the SoC architecture is designed. Hardware acceleration for both filed multiplication and Miller-Rabin primality test is implemented, which largely improves the performance of ECC at the expense of a little cost of area. The SM2 public key cryptographic algorithm is implemented on chip. Based on the HJTC [0.11 μm] eFlash standard cell-library, the area of the accelerator is about [0.6 mm2]. The accelerator can execute 167 operations per second for 192 bit unknown-point multiplication and 94 operations per second for 256 bit in 50 MHz. Experimental results show that the performance per unit area of the accelerator is higher than other approaches.

Key words: elliptic curve, Very Large Scale Integration（VLSI）, point multiplication, [GF(p)], SM2 algorithm

摘要： 分析了素数域椭圆曲线密码（ECC）算法的软件效率，针对软件效率较低的问题，对密码系统进行软硬件划分，提出了一种适用于椭圆曲线密码SoC的硬件加速器设计，并设计了密码SoC的结构。硬件加速器实现了素数域的点乘和素数检测，以少量的面积为代价提升了系统性能。密码芯片实现了SM2商用密码标准规定的6种算法。加速器基于HJTC [0.11 μm] eFlash单元库，面积约为[0.6 mm2]。在50 MHz的频率下，192 bit非固定点乘运算性能为167次/s，256 bit非固定点乘运算性能为94次/s。实验结果表明，该加速器的单位面积性能高于其他同类设计。

关键词: 椭圆曲线, 超大规模集成电路（VLSI）, 点乘, 素数域, SM2算法