Abstract: IP （Intellectual Property） reuse is a critical technology for shortening design cycle and reducing design cost of the chip. However, it is easily attacked by illegal users in real-world IP protection. In this paper, a robust IP watermarking algorithm based on bitfile is proposed. The random sequence is generated for determining positions of unused LUTs, which are used to insert watermarks. The information for LUTs in bitfile are scattered for insertion of different watermarks. Once the watermark extraction is activated, it can use the reconfiguration of FPGA （Field Programmable Gate Array） and extract watermarks in corresponding LUTs in order. The experimental results on Virtex XCV600-6bg432 show that the proposed algorithm has no impact on logic function of IP circuit and is superior in strengthened robustness and has low （resource） overhead by comparing with other algorithms.

Key words: Intellectual Property（IP） reuse, Field Programmable Gate Array（FPGA）, Look Up Table（LUT）, Intellectual Property（IP） watermarking

摘要： 数字芯核可复用技术是缩短芯片设计周期和降低芯片设计成本的关键，然而这种技术在芯核知识产权保护的实际应用中往往容易受到非法攻击者的攻击威胁，提出一种基于比特流文件的鲁棒芯核水印算法，该算法主要通过随机序列来确定水印信息嵌入空闲LUT的位置，利用比特流文件中LUT的信息表来分散的隐藏不同的水印信息；当水印信息需要进行提取时，可以利用FPGA中可重构的特点，将水印信息依次从FPGA的LUT位置中重构提取出来。从Virtex XCV600-6bg432平台上的验证结果表明，在保证整个芯核水印电路逻辑功能不受影响的前提下，该方法相比其他的方法具有鲁棒性较强以及（资源）开销较低等优点。

关键词: 芯核复用技术, 现场可编程门阵列（FPGA）, 查找表, 芯核水印