Abstract: A circuit rewriting instruction system is designed and a FPGA pack method Dup-Pack based on CSPack is presented. It only needs to?change?instruction flow?description file, Dup-Pack can implement packing for different FPGA chip. It?replaces?the derivative function cell in user circuit netlist with standard function cell, packs the standard function cell, so the number of sample circuits reduction is achieved with implement of the advanced logic function packing. Experimental results show that Dup-Pack compared with T-VPack achieves 11.26% reduction in chip area, and the speed of pack improves 2.77 times compared to the traditional CSPack when implementing the same logic function packing.

Key words: pack, circuit rewrite, standard function circuit, Field Programmable Gate Array（FPGA）

摘要： 设计了一种电路改写指令系统，并在CSPack算法的基础上提出了一种新的FPGA装箱方法Dup-Pack。Dup-Pack只需要改动指令流描述文件，就能实现对不同FPGA芯片的装箱。该方法采用将用户电路网表中的衍生逻辑单元替换为标准逻辑单元，再对标准逻辑单元进行装箱的方式，在实现高级逻辑功能装箱的情况下减少了样本电路总数。实验结果表明Dup-Pack的装箱结果相比较于T-VPack可减少11.26%的面积，在完成相同逻辑功能的情况下，较传统CSPack装箱速度提升2.77倍。

关键词: 装箱, 电路改写, 标准功能电路, 现场可编程门阵列