Computer Engineering and Applications ›› 2011, Vol. 47 ›› Issue (35): 81-83.

• 研发、设计、测试 • Previous Articles     Next Articles

Design of 5.2 GHz power amplifier implementation in CMOS technology

LIU Gaohui,MA Xiaobo   

  1. School of Automation & Information Engineering,Xi’an University of Technology,Xi’an 710048,China
  • Received:1900-01-01 Revised:1900-01-01 Online:2011-12-11 Published:2011-12-11

5.2 GHz CMOS功率放大器设计

刘高辉,马晓波   

  1. 西安理工大学 自动化与信息工程学院,西安 710048

Abstract: WLAN power amplifier of two-stage differential structure is designed for 5.2 GHz,which adopts TSMC 0.18 μm CMOS technology.In order to improve its linearity and power added efficiency,inductors are introduced between each differential amplifier stage Cascode circuit,and some series-parallel MOS transistors are introduced at every level within the Cascode amplifiers.By using ADS2009 and Cadence software,the layout of the power amplifier circuits are drawn that have been completing design and simulation.The simulation shows that under the 1.8 V working voltage,the output power is 19.6 dBm,the power gain is 28.2 dB,the PAE is 18.1% in the 1 dB compression point.It can be adopted in the wireless LAN 802.11a standard systems.

Key words: CMOS, Wireless Local Area Networks(WLAN), power amplifier, layout

摘要: 采用TSMC 0.18 μm CMOS工艺设计了一个5.2 GHz WLAN(无线局域网)的功率放大器,该放大器采用两级差分结构。为了提高其线性度和功率附加效率,在每个差分放大级共源共栅电路之间引入电感,以及在每一级共源共栅放大器内部引入了多个MOS管的串并联。在ADS2009软件平台下对该功率放大器进行仿真,并应用Cadence软件进行功率放大器电路的版图设计。仿真结果表明,在1.8 V工作电压下,1 dB压缩点输出功率为19.6 dBm,增益为28.2 dB,功率附加效率为18.1%,符合无线局域网802.11a标准系统的要求。

关键词: CMOS, 无线局域网, 功率放大器, 版图